The speed at which many processors operate is often measured in cycles per second or at a clock frequency f. The period T of the clock is the reciprocal 1/f of the frequency. The frequency f of a processor is usually limited by the longest delay path (often called a critical path) between one memory element (e.g. a register) and another memory element. A delay path, for example, includes the time it takes for data to leave a first memory element, propagate through a logic block, and be stored in a second memory. A logic block may perform various operations. For example a logic block may perform operations such as adding numbers, comparing numbers or multiplying numbers.
The clock frequency f may be increased using several techniques. For example, the clock frequency f may be increased by making transistors that are used in memory elements and logic blocks switch faster. These transistors may be made to switch faster by making them smaller in selected dimensions (e.g. gate length of a MOSFET (metal oxide semiconductor field-effect transistor)). Reducing the size of transistors also allows more circuits to be included on a chip. Including more circuits on a chip may make the chips less costly.
Another technique that may be used to increase clock frequency f is to reduce the number of logic elements (e.g. NANDs, NORs, multiplexers etc.) in a delay path required to perform a function. Various techniques may be used to reduce the number of logic elements in a delay path used to perform a function. For example, a Karnaugh map may be used to reduce the number of logic elements needed to perform a function.
Some functions, for example multiplication and division, may require more than one clock cycle to be fully executed. The number of clock cycles required to perform a function may also be reduced by reducing the longest delay path from one memory element, through a logic block, and into a second memory block. Reducing the longest delay path may allow more calculations to done in a single clock cycle and as a result may reduce the number of clock cycles needed to perform a function such as multiplication.